View W83194BR-P4X_328759.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W83194BR-P4X STEPLESS VIA P4X/P4M MAIN CLOCK GENERATOR
Date:
02/21/2003
Revision: 2.0
W83194BR-P4X Data Sheet Revision History
NO. 1 2 Pages n.a. n.a. 4,10 3 7/01/2002 8/07/2002 1.0 1.1 Dates Version Web Version n.a. n.a 1.1 Main Contents All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0 FS1 internal 120K pull up change to pull down. Register 3: bit 0,1 PCISTOPB read back & CPUSTOPB read back exchange. 5 All 9/19/2002 2/21/2003 1.2 2.0 1.2 2.0 Change version and version on web site to 1.1 VTTPWGD# This pin is LOW active. Update new form
4 5 6 7 8 9 10
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
TABLE OF CONTENT
1. GENERAL DESCRIPTION ..................................................................................... 1 2. PRODUCT FEATURES .......................................................................................... 1 3. BLOCK DIAGRAM ................................................................................................. 2 4. PIN CONFIGURATION........................................................................................... 2 5. PIN DESCRIPTION................................................................................................. 3
5.1 CRYSTAL I/O ........................................................................................................................................ 3 5.2 CPU, AGP, AND PCI, IOAPIC CLOCK OUTPUTS............................................................................. 3 5.3 I2C CONTROL INTERFACE................................................................................................................. 4 5.4 FIXED FREQUENCY OUTPUTS......................................................................................................... 4 5.5 POWER MANAGEMENT PINS............................................................................................................ 4 5.6 POWER PINS........................................................................................................................................ 5 5.7 HARDWARE MULTSEL [1:0] SELECTS FUNCTION......................................................................... 5
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ............................ 6 7. I2C CONTROL AND STATUS REGISTERS........................................................... 7
7.1 REGISTER 0: FREQUENCY SELECT REGISTER (DEFAULT = 0) ................................................. 7 7.2 REGISTER 1: CPU CLOCK REGISTER (1 = ENABLE, 0 = STOPPED) .......................................... 7 7.3 REGISTER 2: PCI CLOCK REGISTER (1 = ENABLE, 0 = STOPPED) ............................................ 7 7.4 REGISTER 3: PCI, REF, 48MHZ CLOCK REGISTER (1 = ENABLE, 0 = STOPPED) .................... 8 7.5 REGISTER 4:MULTISEL1 IOAPIC, AGP CONTROL REGISTER (1 = ENABLE, 0 = STOPPED).. 8 7.6 REGISTER 5: WATCHDOG CONTROL REGISTER ......................................................................... 9 7.7 THE REGISTER 6, 7 IS RESERVED FOR BUFFER.......................................................................... 9 7.8 REGISTER 8: WATCHDOG TIMER REGISTER ................................................................................ 9 7.9 REGISTER 9: M/N PROGRAM REGISTER........................................................................................ 9 7.10 REGISTER 10: M/N PROGRAM REGISTER..................................................................................10 7.11 REGISTER 11: SPREAD SPECTRUM PROGRAMMING REGISTER .........................................10 7.12 REGISTER 12: DIVISOR AND STEP-LESS ENABLE CONTROL REGISTER............................10 7.13 REGISTER 13: CPU TO IOAPIC SKEW CONTROL......................................................................12 7.14 REGISTER 14: CPU TO PCI AND IOAPIC SKEW CONTROL......................................................12 7.15 REGISTER 15: SEL24_48 AND CPU TO CPUCS SKEW CONTROL..........................................12 7.16 REGISTER 16: RESERVED ............................................................................................................13 7.17 REGISTER 17: RESERVED ............................................................................................................13 7.18 REGISTER 18: RESERVED ............................................................................................................13 7.19 REGISTER 19: WINBOND CHIP ID REGISTER (READ ONLY)................................................14 7.20 REGISTER 20: WINBOND CHIP ID REGISTER (READ ONLY)................................................14
8.ACCESS INTERFACE........................................................................................... 15
Publication Release Date: February 2003 Revision 2.0
-I-
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
8.1 BLOCK WRITE PROTOCOL..............................................................................................................15 8.2 BLOCK READ PROTOCOL ...............................................................................................................15 8.3 BYTE WRITE PROTOCOL.................................................................................................................15 8.4 BYTE READ PROTOCOL ..................................................................................................................15
9. SPECIFICATIONS ................................................................................................ 16
9.1 ABSOLUTE MAXIMUM RATINGS.....................................................................................................16
10. ORDERING INFORMATION............................................................................... 16 11. HOW TO READ THE TOP MARKING................................................................ 16 12. PACKAGE DRAWING AND DIMENSIONS ....................................................... 17
- II -
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
1. GENERAL DESCRIPTION
The W83194BR-P4X is a Clock Synthesizer for VIA P4 chipset. W83194BR-P4X provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and AGP clocks setting. All clocks are externally selectable with smooth transitions. The W83194BR-P4X provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-P4X also has watch dog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-P4X accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. The fixed frequency outputs as REF and 48 MHz provide better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
* * * * * * * * * * * * * * * * 2 Differential pairs of CPU clock outputs 1 Differential pairs push pull of CPU_CS clock outputs 3 AGP clock outputs 9 PCI synchronous clocks 24_48Mhz clock output for super I/O. 48 MHz clock output for USB. 2 IOAPIC clock outputs. 1 REF clock output. Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% and +/- 0.25% center type spread spectrum Programmable S.S.T. scale to reduce EMI Programmable registers to enable/stop each output and select modes Watch Dog Timer and RESET# output pins
* 48-pin SSOP package
-1-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
3. BLOCK DIAGRAM
Driver 48MHz
PLL2
1/2
Mux
24_48MHz
XIN XOUT
XTAL OSC VCOCLK
REF
PLL1 Spread Spectrum
Divider /2,/4,/8,/16
3
Stop
3 2
CPUCLK_T 0:1, CS CPUCLK_C 0:1, CS
M/N/Ratio S.S.P ROM
VTTPWRGD# FS<4:0> Latch & POR
/3,/6,/12 /5,/10,/20 /7,/14 /9,/18
Stop
9 3
IOAPIC 0:1
AGP 0:2
PCICLK_F PCICLK_0:7
PD#* PCI_STOP#* CPU_STOP#* MULTISEL0* SEL24_48&
Control Logic & Config Register
I2C interface
RESET#
Rref SDATA* SDCLK*
4. PIN CONFIGURATION
S E L 2 4 _ 4 8 & /R E F VDDREF GND X IN XO UT VDD48 F S 3 & /4 8 M H z F S 2 & /2 4 _ 4 8 M H z GND F S 0 * /P C IC L K _ F F S 1 & /P C IC L K 0 M U L T IS E L 0 */P C IC L K 1 GND P C IC L K 2 P C IC L K 3 VDDPCI P C IC L K 4 P C IC L K 5 P C IC L K 6 GND P C IC L K 7 PD#* AGP0 VDDAGP 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 V D D A P IC (2 .5 V ) GND IO A P IC 0 IO A P IC 1 GND V D D C P U (2 .5 V ) CPUCLKT_CS CPUCLKC_CS CPUCLK_T0 CPUCLK_C0 V D D C P U (3 .3 V ) IR E F GND CPUCLK_T1 CPUCLK_C1 VTTPW RG# CPU_STO P#* P C I_ S T O P # * RESET# SDATA* SDCLK* AGP2 AGP1 GND
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
#: Active low ^: These outputs have 1.5 ~ 2X drive strength *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND
-2-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
5. PIN DESCRIPTION
Buffer type symbol IN INtp120k INtd120k OUT OD I/O I/OD # * & Description Input Latched input at power up, internal 120k pull up. Latched input at power up, internal 120k pull down. Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain. Active Low Internal 120k pull-up Internal 120 k pull-down
5.1 Crystal I/O
PIN 4 5 Pin Name XIN XOUT Type IN OUT Description Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). Description Low skew (< 250ps) differential clock outputs for host frequencies of CPU Low skew (< 250ps) differential push pull clock outputs for host frequencies of CHIPSET 3.3V AGP clock outputs. 3.3V free running PCI clock output.
5.2 CPU, AGP, and PCI, IOAPIC Clock Outputs
PIN 34,35,39,40 41,42 23,26,27 10 Pin Name CPUCLK_T [0:1] CPUCLK_C [0:1] CPUCLKT_CS CPUCLKC_CS AGP0: 2 PCICLK_F FS0* PCICLK0 11 FS1& PCICLK1 12 14,15,17,18, 19,21 45,46 MULTI_SEL0* PCICLK [2:7] IOAPIC0: 1 Type OUT OUT OUT OUT
INtp120k Latched input for FS0 at initial power up for H/W selecting the output frequency. This is internal 120K pull up. OUT 3.3V PCI clock output. INtd120k Latched input for FS1 at initial power up for H/W selecting the output frequency, This is internal 120K pull down. OUT 3.3V PCI clock output. INtp120k Latched input for MULTSEL0 at initial power up, internal 120K pull up OUT OUT Low skew (< 250ps) PCI clock outputs. 2.5V PCI/2 clock outputs.
-3-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
5.3 I2C Control Interface
PIN 25 26 Pin Name SDATA* SDCLK* Type I/OD IN Description Serial data of I2C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor. Description 14.318MHz output. Latched input for 24MHz or 48MHz select pin. This is internal 120K pull down default 24MHz. In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 16 bit 6. 48MHz clock output for USB. Latched input for FS3 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 24(default) or 48MHz clock output, In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 16 bit 7. Latched input for FS2 at initial power up for H/W selecting the output frequency. This is internal 120K pull down.
5.4 Fixed Frequency Outputs
PIN Pin Name REF SEL24_48& 48MHz 7 FS3& 24_48MHz 8 FS2& INtd120k OUT INtd120k OUT Type OUT INtd120k
1
5.5 Power Management Pins
PIN 33 32 31 Pin Name VTTPWGD# CPU_STOP#* PCI_STOP#* IN IN IN 37 IREF Type IN Description Power good input signal comes from ACPI with LOW active. This 3.3V input is level sensitive strobe used to determine FS [4:0] and MULTISEL input are valid and is ready to sample. This pin is LOW active. CPU clock stop control pin, This pin is low active. Internal 120k pull-up. PCI clock stop control pin, This pin is low active. Internal 120k pull-up. Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. There are several modes to select different current via power on trapping the Pin 12 (MULTISEL). The table is show as follows. System reset signal when the watchdog is time out. This pin will generate 250ms low phase when the watchdog timer is timeout. Power Down Function. This is power down pin, low active (PD#). Internal 120K pull up
30 22
RESET# PD#*
OD IN
-4-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
5.6 Power Pins
PIN 2 16 24 38 43 48 6 3,9,13,20,25, 36,44,47 Pin Name VDDREF VDDPCI VDDAGP VDDCPU VDDCPU_CS VDDAPIC VDD48 GND Type PWR PWR PWR PWR PWR PWR PWR PWR Description 3.3V power supply for REF. 3.3V power supply for PCI. 3.3V power supply for AGP. 3.3V power supply for CPU. 2.5V power supply for CPUCLKT & C _CS. 2.5V power supply for IOAPIC. Analog power 3.3V for 48MHz. Ground pin for 3.3 V
5.7 Hardware MULTSEL [1:0] selects Function
Multsel1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Multsel0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 Board Target trace/Term Z 50 60 50 60 50 60 50 60 50 60 50 60 50 60 50 60 Reference R, IREF = Add/(3*Rr) Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Output Current Ioh=4*IREF Ioh=4*IREF Ioh=5*IREF Ioh=5*IREF Ioh=6*IREF Ioh=6*IREF Ioh=7*IREF Ioh=7*IREF Ioh=4*IREF Ioh=4*IREF Ioh=5*IREF Ioh=5*IREF Ioh=6*IREF Ioh=6*IREF Ioh=7*IREF Ioh=6*IREF Voh @ Z 1.0V @ 50 1.2V @ 60 1.25V @ 50 1.5V @ 60 1.5V @ 50 1.8V @ 60 1.75V @ 50 2.1V @ 50 0.47V @ 50 0.56V @ 50 0.58V @ 50 0.7V @ 60 0.7V @ 50 0.84V @ 60 0.81V @ 50 0.97V @ 60
-5-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software [4:0] (Register 0 bit 6 ~ 2). FS4 FS3 FS2 FS1 FS0 CPU (MHZ) AGP (MHZ) PCI (MHz) IOAPIC 0 0 0 0 0 66.7 66.66 33.33 0 0 0 0 1 100.0 66.67 33.335 0 0 0 1 0 133.3 66.67 33.335 0 0 0 1 1 200.0 66.66 33.33 0 0 1 0 0 100.9 67.27 33.635 0 0 1 0 1 103.0 68.67 34.335 0 0 1 1 0 107.0 71.33 35.665 0 0 1 1 1 110.0 73.33 36.665 0 1 0 0 0 133.9 66.95 33.475 0 1 0 0 1 137.3 68.66 34.33 0 1 0 1 0 140.0 70 35 0 1 0 1 1 142.7 71.33 35.665 0 1 1 0 0 145.3 72.66 36.33 0 1 1 0 1 146.7 73.33 36.665 0 1 1 1 0 153.3 76.66 38.33 0 1 1 1 1 160.0 80 40 1 0 0 0 0 66.7 66.66 33.33 1 0 0 0 1 100.0 66.67 33.335 1 0 0 1 0 133.3 66.67 33.335 1 0 0 1 1 200.0 66.66 33.33 1 0 1 0 0 66.7 66.66 33.33 1 0 1 0 1 100.0 66.67 33.335 1 0 1 1 0 133.3 66.67 33.335 1 0 1 1 1 200.0 66.66 33.33 1 1 0 0 0 201.0 67 33.5 1 1 0 0 1 203.0 67.67 33.835 1 1 0 1 0 205.0 68.33 34.165 1 1 0 1 1 207.0 69 34.5 1 1 1 0 0 209.0 69.67 34.835 1 1 1 0 1 211.0 70.33 35.165 1 1 1 1 0 213.0 71 35.5 1 1 1 1 1 215.0 71.67 35.835 programming at SSEL (MHz) Spread % 16.665 +/-0.25% 16.668 +/-0.25% 16.668 +/-0.25% 16.665 +/-0.25% 16.818 +/-0.25% 17.168 +/-0.25% 17.833 +/-0.25% 18.333 +/-0.25% 16.738 +/-0.25% 17.165 +/-0.25% 17.5 +/-0.25% 17.833 +/-0.25% 18.165 +/-0.25% 18.333 +/-0.25% 19.165 +/-0.25% 20 +/-0.25% 16.665 -0.5% 16.668 -0.5% 16.668 -0.5% 16.665 -0.5% 16.665 +/-0.25% 16.668 +/-0.25% 16.668 +/-0.25% 16.665 +/-0.25% 16.75 +/-0.25% 16.918 +/-0.25% 17.083 +/-0.25% 17.25 +/-0.25% 17.418 +/-0.25% 17.583 +/-0.25% 17.75 +/-0.25% 17.918 +/-0.25%
-6-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
7. I2C CONTROL AND STATUS REGISTERS
7.1 Register 0: Frequency Select Register (default = 0)
Bit 7 6 5 4 3 EN_SSEL 2 1 EN_SPSP 0 EN_SAFE_FREQ SSEL [4] Name SSEL [3] SSEL [2] SSEL [1] SSEL [0] PWD Description 0 0 0 0 0 Enable software program FS [4:0]. 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 7~ 4,2. Frequency selection bit 4 Enable Spread Spectrum in the frequency table. 0 = Normal 1 = Spread Spectrum enabled Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 5 bit 4~0. Frequency selection by software via I2C
0 0
0
7.2 Register 1: CPU Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 Pin NO 42,41 35,34 40,39 PWD Description 1 1 1 X X X X X CPUCLK_T / C_CS CPUCLK_T1 / C1 CPUCLK_T0 / C0 FS [4] Read back. FS [3] Read back FS [2] Read back FS [1] Read back FS [0] Read back
7.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 Pin NO 21 19 18 17 15 14 PWD Description 1 1 1 1 1 1 PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2
-7-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
1 0 12 11 1 1 PCICLK1 PCICLK0
7.4 Register 3: PCI, REF, 48MHz Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 Pin NO 7 8 1 10 41,42 8 32 31 PWD Description 1 1 1 1 1 0 1 1 48MHZ 24_48MHz REF PCICLK_F CPUCS Stop control: 0: CPUCLK1 free run 1: CPUCLK1 can stopped by CPU_STOP# PCI_F Stop control 0: PCI_F free run 1: PCI_F can stopped by PCI_STOP# PCISTOPB read back CPUSTOPB read back
7.5 Register 4:MULTISEL1 IOAPIC, AGP Control Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 Pin NO 45 46 27 26 23 PWD Description 0 1 1 1 1 1 1 1 MULTISEL1 I2C R/W Reserved Reserved IOAPIC1 IOAPIC0 AGP2 AGP1 AGP0
-8-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
7.6 Register 5: Watchdog Control Register
Bit 7 6 Name MULTISEL0 EN_WD PWD Description X 0 Pin 12 MULTISEL0 power on trapping pin data read back Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only.
5
WD_TIMEOUT
0
4 3 2 1 0
SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0]
0 0 0 0 0 Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits.
7.7 The Register 6, 7 is reserved for Buffer 7.8 Register 8: Watchdog Timer Register
Bit 7 6 5 4 3 2 1 0 Name WD_TIME [7] WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1] WD_TIME [0] PWD Description 0 0 0 0 1 0 0 0 Watchdog timeout time. The bit resolution is 250mS. The default time is 8*250mS = 2.0 seconds. If the watchdog timer is start, this register will be down count. Read this register will return a down count value.
7.9 Register 9: M/N Program Register
Bit 7 6 5 4 3 2 1 0 Name N_DIV [8] TEST2 TEST1 M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0] PWD Description 1 0 1 0 1 1 0 1 Programmable M divisor value. Programmable N divisor value. Bit 7 ~0 are defined in the Register 10. Test bit 2. Winbond test bit, do not change them. Test bit 1. Winbond test bit, do not change them.
-9-
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
7.10 Register 10: M/N Program Register
Bit 7 6 5 4 3 2 1 0 Name N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0] PWD 0 1 1 0 0 1 1 1 Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 9. Description
7.11 Register 11: Spread Spectrum Programming Register
Bit 7 6 5 4 3 2 1 0 Name SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0] PWD Description 0 0 0 1 1 1 1 1 Spread Spectrum Up Counter bit 3. Spread Spectrum Up Counter bit 2. Spread Spectrum Up Counter bit 1. Spread Spectrum Up Counter bit 0 Spread Spectrum Down Counter bit 3 Spread Spectrum Down Counter bit 2 Spread Spectrum Down Counter bit 1 Spread Spectrum Down Counter bit 0
7.12 Register 12: Divisor and Step-less Enable Control Register
Bit Name 7 EN_MN_PROG PWD Description 0 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 0 bit 0). CPU, PCI, AGP, ratio selection. The ratio is shown as following table.
6 RATIO_SEL [4] 5 RATIO_SEL [3] 4 RATIO_SEL [2] 3 RATIO_SEL [1] 2 RATIO_SEL [0] 1 TEST0 0 Reserved
0 0 0 1 0 0 0 Test bit 0. Winbond test bit, do not change them.
- 10 -
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
I2C Reg12 Definition
Reg12 Reg12 Reg12 Reg12 Reg12 Bit6 Bit5 Bit4 Bit3 Bit2 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 CPU CPU_CS IOAPIC ratio 2 3 4 6 4 4 4 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 2 3 4 6 2 2 4 4 ratio 2 3 4 6 4 4 4 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 2 3 4 6 2 2 4 4 ratio 24 24 24 24 24 24 24 24 24 16 16 24 24 16 20 16 20 20 20 24 16 14 18 14 16 24 16 16 14 18 14 18 AGP ratio 6 6 6 6 6 6 6 6 6 8 8 6 6 8 10 8 10 10 10 6 8 7 9 12 8 12 8 8 7 9 7 9 PCI ratio 12 12 12 12 12 12 12 12 12 16 16 12 12 16 20 16 20 20 20 12 16 14 18 14 16 24 16 16 14 18 14 18
- 11 -
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
7.13 Register 13: CPU to IOAPIC SKEW CONTROL
Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Name PWD Description 1 CPU to IOAPIC SKEW control CPU_IOAPIC_SKEW [2] Reserved 0 Reserved Reserved 1 Reserved for Winbond internal use, do not change them Reserved 0 Reserved 0 Reserved 1 Reserved 1 Reserved 1 Name PWD CPU_PCI_SKEW [2] 1 CPU_PCI_SKEW [1] 0 CPU_PCI_SKEW [0] 0 CPU_AGP_SKEW [2] 1 CPU_AGP_SKEW [1] 0 CPU_AGP_SKEW [0] 0 CPU_IOAPIC_SKEW [1] 0 CPU_IOAPIC_SKEW [0] 0 Description CPU to PCI skew
7.14 Register 14: CPU to PCI and IOAPIC Skew Control
CPU to AGP Skew
CPU to IOAPIC SKEW control
7.15 Register 15: SEL24_48 and CPU to CPUCS skew Control
Bit 7 Name SEL24_48 PWD Description X In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. 0-> 24 MHz, 1->48MHz. Default is 24Mhz Reserved Reserved for Winbond internal use, do not change them Reserved for Winbond internal use, do not change them CPU to CPUCS Skew
6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved CPU_CPUCS_SKEW [2] CPU_CPUCS_SKEW [1] CPU_CPUCS_SKEW [0]
0 0 0 0 1 0 0
- 12 -
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
7.16 Register 16: Reserved
Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD Description 1 1 1 1 1 1 1 1 Reserved for Winbond internal use, do not change them Reserved for Winbond internal use, do not change them Reserved for Winbond internal use, do not change them Reserved for Winbond internal use, do not change them
7.17 Register 17: Reserved
Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD 1 1 1 1 1 1 0 0 Reserved for Winbond internal use, do not change them Reserved for Winbond internal use, do not change them Reserved for Winbond internal use, do not change them Description Reserved for Winbond internal use, do not change them
7.18 Register 18: Reserved
Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD 1 1 1 1 1 1 1 1 Reserved Reserved Reserved for Winbond internal use, do not change them Description Reserved for Winbond internal use, do not change them
- 13 -
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
7.19 Register 19: Winbond Chip ID Register
Bit 7 6 5 4 3 2 1 0 Name CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0] PWD Description 0 1 0 1 0 1 1 1 Winbond Chip ID. W83194BR-P4X is 0x57. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
(Read Only)
7.20 Register 20: Winbond Chip ID Register
Bit 7 6 5 4 3 2 1 0 Name SUB_ID [3] SUB_ID [2] SUB_ID [1] SUB_ID [0] VER_ID [3] VER_ID [2] VER_ID [1] VER_ID [0] PWD Description 0 0 0 1 0 0 0 1
(Read Only)
Winbond Sub-Chip ID. The sub-chip ID of W83194BR-P4X is defined as 0010b. Winbond Sub-Chip ID. Winbond Sub-Chip ID. Winbond Sub-Chip ID. Winbond Version ID. The Version ID of W83194BR-P4X is 0001b. Winbond Version ID. Winbond Version ID. Winbond Version ID.
- 14 -
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
The W83194BR-P4X provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-P4X is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol
8.ACCESS INTERFACE
8.1 Block Write protocol
8.2 Block Read protocol
## In block mode, the command code must filled 8'h00
8.3 Byte Write protocol
8.4 Byte Read protocol
- 15 -
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). Parameter Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) Rating -0.5V to +4.6V - 0.5 V to + 4.6 V 3.135V to 3.465V 3.135V to 3.465V - 65C to + 150C - 55C to + 125C 0C to + 70C 2000V
10. ORDERING INFORMATION Part Number W83194BR-P4X Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
11. HOW TO READ THE TOP MARKING
W83194BR-P4X 28051234 214GAB
1st line: Winbond logo and the type number: W83194BR-P4X 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 214: packages made in '2002, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
- 16 -
Publication Release Date: February 2003 Revision 2.0
W83194BR-P4X
STEPLESS CLOCK FOR VIA P4 CHIPSET
12. PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
- 17 -
Publication Release Date: February 2003 Revision 2.0

▲Up To Search▲

Price & Availability of W83194BR-P4X

	To Download W83194BR-P4X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .